In digital data transmission systems operating in an asynchronous data transfer mode, digital data is output by a transmission unit as an asynchronous serial data signal, without an clock signal embedded therein. Upon reception of the asynchronous serial data signal, the receiver must function to recover the data transmitted by the transmission unit, and to generate a clock signal corresponding to the received data. Importantly, both the generated clock signal and the data must be synchronous (i.e., phase aligned) with one another so as to allow the receiver to properly process the received data.
FIG. 1 illustrates an example of a prior art clock and data regeneration portion of a receiver circuit. As shown, the receiver 10 has a cable 8 coupled to the input thereof. Cable 8 functions to couple the asynchronous data signal to the receiver. The clock and data regeneration portion 12 of the receiver comprises a clock recovery unit 13 and a sampling gate 14, which, for example, can comprise a latch or flip-flop. In operation, the incoming serial data signal is coupled to the clock recovery unit 13, which functions to reproduce a clock signal corresponding to the received data signal. The output of the clock recovery unit 13 is coupled to a clock input of the sampling gate 14, and is utilized to clock the sampling gate 14. As such, the output of the sampling latch 14 and the clock recovery unit 13 represent the incoming data signal and corresponding clock signal phase aligned with one another. These two signals, which represent the output of the clock and data regeneration portion 12 of the receiver, are coupled to the main portion of the receiver for processing.
FIG. 2 illustrates an example of one known clock recovery unit 16. As shown, the clock recovery unit comprises a phase detector 17, a charge pump 18, a low pass filter 19 and a voltage controller oscillator (“VCO”) 20 all coupled in series. In operation, the phase detector 17 receives both the incoming serial data signal and the output of the VCO 20 as input signals, and detects the phase difference between these two signals. The phase difference output by the phase detector 17 is then utilized to control the voltage level output by the charge pump 18 so as to adjust the frequency of the signal output by the VCO 20 to eliminate the phase difference between the VCO 20 and the incoming serial data signal. Accordingly, the output of the VCO 20 is continuously tracking the incoming serial data signal and represents the recovered clock signal.
However, as the clock recovery unit 16 is essentially a phase-lock loop, it takes approximately 1:sec. or more to synchronize the clock signal to the data signal having a frequency of, for example, that utilized by the USB 2.0 standard. During this “synchronization” period incoming data cannot be recovered, and therefore the data is lost.
Another method of recovering the clock signal corresponding to the incoming asynchronous data signal is to over-sample the incoming data signal. For example, 4× oversampling can be utilized to recover the corresponding clock signal. However, while such an approach is acceptable for low frequency signals, it is not a practical solution for high frequency signals (e.g., 500 Mbit/sec. signal). In particular, it is not practical to implement a clock having the necessary 4× frequency in an IC. Moreover, such a high frequency clock source introduces undesirable noise problems into the circuit.
Accordingly, there is exists a need for a method and a system for generating a clock signal corresponding to an asynchronous data signal that solves the foregoing problems. More specifically, a method and a system that allows for fast synchronization of the incoming data signal and clock signal so as to minimize the loss of incoming data, and that does not require a sampling source having a frequency rate greater than that of the incoming data signal.